Over the past several decades, the electronics field has been moving rapidly toward using digital techniques for handling information. In particular, signals that are initially analog signals are being digitized to allow those signals to be managed, processed and otherwise handled in the digital domain. The advantages of handling signals in the digital domain which have driven this movement are well known to those skilled in the art.
As a consequence of the desire to handle signals in the digital domain, there is a need for analog to digital converters (ADCs) to convert analog signals to the digital signals (i.e., to digitize such analog signals). One type of analog to digital converter, called a successive approximation register (SAR) ADC uses a series of iterative steps to determine a digital value that represents the amplitude of an analog signal.
FIG. 1A is a simplified schematic of a conventional SAR ADC 100. The SAR ADC 100 comprises a successive approximation register (SAR) 102, a digital to analog converter (DAC) 104, a comparator 106 and a track and hold amplifier circuit (THA) 108. An input signal 110 is applied to the THA 108. The THA 108 outputs a signal having a stable amplitude equal to the amplitude of the input signal 110 averaged over the time the sample was taken. The output signal 109 from the THA 108 is then applied to the positive input of the comparator 106. The negative input to the comparator 106 is coupled to the analog output of the DAC 104. The analog output 107 of the DAC 104 is determined by the state of the digital value Di, . . . D. applied to the input of the DAC 104. The value Di, . . . D. is output from the SAR 102 to the DAC 104.
When the ADC 100 starts operating, the SAR 102 is initialized to output a digital value that is equal to half the full scale value of the ADC 100. A reference signal 103 applied to the ADC 100 from an external source defines the magnitude of the full scale output. The most significant bit (MSB) of the SAR (Do) is set to 1 and each of the other bits (D1, D2, . . . Dn_1) are set to 0. Accordingly, the DAC 104 will output a signal with an amplitude that is half the magnitude of the full scale output. A sample clock 110 provided by the SAR 102 is synchronized with a clock signal 105. The clock signal 105 indicates when the THA 108 is to sample the input 110. Typically, the SAR 102 is a state machine that controls the ADC process.
The comparator 106 compares that amplitude of the signal 107 output by the DAC 104 with the amplitude of the sample 109 of the input signal. If the sample 109 has an amplitude greater than or equal to the value output 107 from the DAC 104, then the output 111 from the comparator 106 is set high and applied to the SAR 102. The clock signal 105 sets the timing for the SAR. The sample clock 112 is derived from the clock signal 105. The clock signal 105 to the SAR 102 will indicate when the value output from the comparator is stable. The SAR 102 will then store that value as the value of the MSB. The SAR 102 will then set the next most significant bit DN_1 to 1 and the process repeats until a determination is made for each bit of the SAR output.
Once the value of each bit of the SAR has been determined, an End of Conversion (EOC) signal 114 indicates the completion of the process and the value output by the SAR 102 can be read. This value will then represent the amplitude of the input signal to a resolution determined by the number of bits in the ADC 100 (i.e., the number n of bits output from the SAR 102 and input to the DAC 104).
FIG. 1B is a simplified block diagram of another type of ADC, commonly known as a “pipeline” ADC 101. In a pipeline ADC 101, the conversion from analog to digital format occurs in stages. An input signal 110 is applied to a THA 120 within the first stage. The sampled input 122 is then coupled to the input of a course sub-ADC 124. The sub-ADC 124 provides a three-bit digital representation of the sampled input signal 122. The three-bit output from the sub-ADC 124 is coupled to the input of a multiplying DAC (MDAC) 126. The MDAC 126 converts the three bits back to an analog signal 128. The output 128 is then coupled to a subtraction circuit 129 that subtracts the difference between the output 128 and the sampled input 122. The difference is then applied to an amplifier 131 that provides a gain of 2″, where n is equal to 2 in this case. The amplifier brings the difference back in the range of a second stage of the pipeline ADC 101.
The second stage and each subsequent stage functions identically to the first stage. The output from the sub-ADC 124 of each stage is coupled to a Combine/Process module 130 that combines the output from each stage and does any processing required to correct the output. Other types of ADCs are known as well, including sigma-delta ADCs, etc.
The speed at which current ADCs can operate has been steadily increasing, thus allowing higher and higher frequencies to be digitized. One technique currently used to increase the speed of an ADC involves the use of a set of interleaved individual ADCs.
FIG. 2 is a simplified block diagram of a time interleaved ADC 200. FIG. 3 is a timing diagram for the ADC 200. Time interleaved ADCs use a set of parallel ADCs (frequently referred to as “slices”). Each slice 202, 204, 206, 208 comprises essentially the configuration shown in either FIG. 1A or FIG. 1B. Note that while the examples provided for time interleaved ADCs are shown for SAR ADCs or pipeline ADCs, this would apply for any ADC architecture as well.
Referring to FIG. 3, a master clock 301 runs at a rate that is at least equal to the Nyquist frequency (i.e., twice the highest frequency of the input signal to be digitized). In an ADC 200 that has M slices, a slice sample cycle 303 occurs at the rate at which samples are taken by each slice. In the example shown, Mmaster clock cycles 305 occur during one “sample cycle” 303 at the slice sample rate. In the case shown in FIGS. 2 and 3, there are four slices. Each slice runs at the master clock rate fN divided by the number of slices M (i.e., fN/M). Accordingly, the slice sample rate 303 is one fourth the master clock rate. In addition, each slice is offset in phase by 1/M with a duty cycle that is equal to 1/M. In some cases, the slice clocks run at a 50% duty cycle and the sample time is triggered by an edge of the slice clock and lasts only for that portion of the time during which the other slices are not sampling (i.e., each slice samples for 1/M of the total sample cycle).
Upon completing the conversion of the analog input signal to a digital output from each slice, the output is coupled to a Reconstruction Interleaver 218 which combines the outputs to form a coherent output that digitally represents the analog input signal 110. That is, the output 210, 212, 214, 216 of each slice is interleaved to create a digital representation of one sample cycle of the analog signal 110.
Accordingly, the rate at which the data can be sampled is increased by a multiple equal to the number of slices provided. That is, if M individual ADCs are interleaved, then the rate of the time interleaved ADC is M times the rate of each slice.
One problem that results from the use of time interleaved ADCs is that a correction has to be added to the output 210, 212, 214, 216 of each slice to correct for differences in the gain and offset of each slice 202, 204, 206, 208. That is, differences in the gain and offset of the various slices will cause distortion in the overall output of the time interleaved ADC 200. In addition, differences in sample time also cause distortion.
One way in which the prior art attempts to resolve this problem is to provide a reference slice that samples the input at the same time as the other slices. Since the problem is due to differences in gain and offset between the slices, the problem can be resolved by making the gain and offset of each slice equal. By using an independent slice as a reference, the gain and offset of each slice can be normalized to a value that is the same for each slice with respect to the reference slice. Accordingly, distortion in the interleaved output of an ADC can be reduced.
FIG. 4 is a simplified block diagram of an interleaved ADC 400 with a reference slice 401.
FIG. 5 is a timing diagram of the interleaved ADC 400 shown in FIG. 4.
The reference slice 401 samples the input signal at the same time as one of the active slices 402, 404, 406, 408. The term “active” is used merely to distinguish those slices termed “active slices” that generate the digitized output signal from the reference slice.
The reference slice 401 runs at a slower speed than the active slices 402, 404, 406, 408. In FIG. 5, the reference slice clock 501 runs approximately one half the speed of the active slice clocks 511, 513, 515, 517. Accordingly, the first two samples are taken by the reference slice 401 M master clock cycles apart and concurrent with the samples taken at times 519, 521 by the first active slice 402. As shown in FIG. 5, M is equal to 8. This causes the reference slice 401 to take a first sample at a first reference sample time 503 that is concurrent with a first active sample time 519 taken by the first active slice 402. A second sample is taken by the reference slice 401 at a second reference sample time 505 concurrent with a third sample taken by the first active slice 402 at a third sample time 521. In other cases, M is equal to 12, 16 or any other multiple of the number of active slices, depending upon how much slower the reference slice is with respect to the active slices.
In the case shown in FIG. 5, the reference slice 401 takes two samples concurrent with the first active slice 402. The reference slice 401 then waits M+1 cycles before taking the next sample at reference sample time 507. Waiting one additional cycle, shifts the reference sample time to be concurrent with the sample time 523 of the next active slice 404. The reference slice 401 takes two samples concurrent with each active slice and moves on to the sample time of the next active slice. Therefore, the reference slice 401 rolls through the active slice sample times in round robin fashion. The fact that the reference slice 401 need not sample at a high rate is advantageous, since reducing the processing speed of the reference slice reduces the cost and the amount of power required to operate the ADC 400. In the example of FIG. 5, the reference slice 401 takes two samples concurrent with the each active slice before taking samples concurrent with the next active slice. Alternatively, for a slower reference slice, M can be a multiple of four greater than 8. Accordingly, the reference slice 401 takes a sample once for every M/4 times that the active slice 401 takes a sample.
It should be noted that a reference THA (not shown) will track the sample for the same amount of time as, and concurrent with, one of the active THAs (not shown). This is so even though the reference slice 401 processes the sample slower. Furthermore, in one example, the reference slice 401 takes 8 reference samples over 128 master clock cycles (i.e., one every 16 clock cycles over 128 clock cycles), rather than just 2 samples over 16 master clock cycles, as shown in FIG. 5. In this case, it should be noted that the first active slice 402 will take 4 samples for each one sample taken by the reference slice 401. Those 8 reference samples are digitized and each resulting digital output is compared to the corresponding digital output resulting from the slice sample taken at the same time by the first active slice 402. The differences between the 8 reference measurements and the 8 active slice samples can then be averaged (or otherwise weighted and combined) to determine the difference between the first active slice 402 and the reference slice 401. After taking the 8 reference samples concurrent with the first active slice 402, the reference sample time of the reference slice 401 is shifted by one master clock cycle to coincide with the slice sample time of the second active slice 404. Once again, the reference slice 401 will take 8 reference samples over a period of 128 slice sample cycles (one every 16 slice sample cycles) concurrent with the samples taken by the second active slice 404. This will be repeated for the other two active slices 406, 408.
The Reconstruction Interleaver 410: (1) receives the output from the reference slice; (2) receives the output from each of the active slices 402, 404, 406, 408; and (3) calculates a correction to be applied to each of the active slices 402, 404, 406, 408 based on the average difference between the sample taken by the reference slice and the sample taken by the active slice at the same time.
It should be noted that the order in which the active slices 402, 404, 406, 408 sample the input can be pseudo random or may follow a pattern other than what is shown.
One problem with this approach is that the loading of the input signal (i.e., the loading on the input to each slice 402, 404, 406, 408) changes when the reference slice 401 is sampling the input in coincidence with sampling by an active slice 402, 404, 406, 408. This causes the value of the sample taken by the active slices 402, 404, 406, 408 to be slightly different from the value of that would have been sampled without the loading of the reference slice 401. This difference causes distortion due to the difference between the values of the samples from sample to sample. That is, in the example shown in FIG. 5, the reference slice 401 only samples the signal once for every two samples taken by the active slice. Therefore, there is a difference in the load on the input of each active slice 402, 404, 406, 408 when the reference slice 401 is sampling concurrent with an active slice 402, 404, 406, 408 and when the reference slice 401 is not sampling concurrent with an active slice 402, 404, 406, 408.
In addition, there is a difference in the measurement taken when the reference slice 401 is sampling concurrent with the first active slice 402 and the time the reference slice 401 is sampling concurrent with the second active slice 404, etc. Accordingly, there is presently a need for an ADC that can perform fast digitization of high frequency analog signals while reducing the resulting distortion.